A General Purpose FPGA Data Filter for Data Stream Processing
نویسندگان
چکیده
The DFU is based on a commodity DRC platform DS2004, containing two AMD Opteron 2350 quad core processors and two Opteron socket compatible DRC Reconfigurable Processor Units (RPUs), all of which are connected via Hypertransport interconnects. Internal Components of the DFU: 1. HT Interface: Used to decode the HT read/write signals to internal DFU components 2. Statistics Registers: Tuples Processed Register (TPR), Stall Count Register (SCR), and Sequential Execution Count Register (SECR) 3. Input/Output FIFOs: Used to write input data streams, read output data streams 4. Program Configuration Module: Controls the program running on the multi-issue execution engine. Also used to preload program constants into the DRF 5. Instruction Issue Stage: Used to issue a wide 659-bit VLIW instruction to 14 computation units 6. Multi-issue execution engine: VLIW microarchitecture with the Distributed Register File (DRF) Multi-issue Execution Engine
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